The electronics industry is under constant pressure to both reduce component size as well as power requirements. One approach to reduce component size is to fabricate devices in a three-dimensional (3D) configuration. For example, a memory device can be arranged as a stack of memory cells vertically on a substrate, as a plurality of interconnected memory dies stacked vertically within a single integrated circuit package, or some combination of these configurations.
Multiple stacked dies in an integrated package can be coupled (e.g., electrically connected) using vertical connectors, such as through substrate vias or other 3D conductive structures. Vias extend (at least partially) through a thickness of one or more of the dies and can be aligned when the dies are stacked, thus providing electrical communication among the dies in the stack. Such vias are often formed of a conductive material, such as aluminum or copper. Improvements in timing signal precision can be useful as device speeds and density increase.